UB Chrinovic

Microarchitectural Determinants of Virtual Machine Performance

Some time ago i posted a tweet. Though, that statement is an oversimplification so in this article i will expand on the idea but from a less abstracted perspective, focusing purely on a microarchitectural and hypervisor-level factors that influence VM performance. This article is a case study on hardware-assisted virtualization with a primary focus on Intel VT-x.

Introduction

The performance profile of a virtual machine is the result of a complex synchronization between physical resource availability, hypervisor orchestration logic, and the specific microarchitectural constraints of the underlying hardware. In modern data centers, virtualization efficiency is governed by the latency of hardware transitions, the depth of address translation walks, and the isolation of shared execution resources. This analysis explores the low-level determinants of virtual machine performance, focusing on the silicon-level features of Intel VT-x.

Public enemy No 1: VM Transitions

The fundamental unit of overhead in hardware-assisted virtualization is the the transitions between the VMM(hypervisor) and guest machine virtual machine. This transition occurs when control and execution switches from the hypervisor context to the guest virtual machine. The transition from the hypervisor to the guest is called a VM Entry, while the switch from the guest back to the hypervisor is called a VM Exit.

Mechanics of VM Exit

A VM exit occurs when the guest executes an instruction or encounters an event that requires hypervisor intervention to preserve isolation and security. This is triggered by sensitive operation, such as privilege instructions(e.g IO/, CPUID, modifications to control registers like CR3 for page table switches), interrupts, exceptions or memory accesses that violate virtualizaion rules. Upon the detection , the processor saves the guest's state into the Virtual Machine Control Structure(VMCS) and restores the host's state, transferring control to the hypervisor.

When the transition occurs, the hypervisor analyzes the exit reason by reading the VMCS's EXIT_REASON/0x4402 field which encodes why the guest triggered a VM exit, performs the necessary actions such as trap-and-emulated the instruction, handling the interrupts, etc. This process incurs latency because it is CPU-intensive due to pipeline flushes, microarchitectural state save/restores, heavy memory operations, guest emulations.